1. Field of the Invention
This invention relates in general to the field of microelectronics, and more particularly to a technique for incorporating selective results write back control features into an existing microprocessor instruction set architecture.
2. Description of the Related Art
Since microprocessors were fielded in the early 1970's, their use has grown exponentially. Originally employed in the scientific and technical fields, microprocessor use has gravitated from those specialty fields into commercial consumer fields that include products such as desktop and laptop computers, video game controllers, and a host of other common household and business devices.
Along with this explosive growth in use over the past 30 years, the art has experienced a corresponding technology pull that is characterized by an escalating demand for increased speed, expanded addressing capabilities, faster memory accesses, larger operand size, more operations (e.g., floating point, single-instruction multiple data (SIMD), conditional moves, etc.), and added specialty operations (e.g., multi-media operations). This technology pull has resulted in an incredible number of advances in the art which have been incorporated in microprocessor designs such as extensive pipelining, super-scalar architectures, cache structures, out-of-order processing, burst access, branch predication, and speculative execution. Quite frankly, a present day microprocessor is an amazingly complex and capable machine in comparison to its 30-year-old predecessors.
But unlike many other products, there is another very important factor that has constrained, and continues to constrain, the evolution of microprocessor architecture. This factor, legacy compatibility, moreover accounts for a great deal of complexity in a present day microprocessor. For market-driven reasons, many producers have opted to incorporate new architectural features into updated microprocessor designs, but at the same time in these newer products they choose to retain all of the capabilities that are required to insure compatibility with older, so-called legacy application programs.
Nowhere has this legacy compatibility burden been more noticeable than can be seen in the development history of x86-compatible microprocessors. It is well known that a present day virtual-mode, 32-/16-bit x86 microprocessor is still capable of executing 8-bit, real-mode, application programs which were produced during the 1980's. And those skilled in the art will also acknowledge that a significant amount of corresponding architectural “baggage” is carried along in the x86 architecture for the sole purpose of supporting compatibility with legacy applications and operating modes. Yet, while in the past developers have been able to incorporate newly developed architectural features into existing instruction set architectures, the means whereby use of these features is enabled—programmable instructions—are becoming scarce. More succinctly, there are no more “spare” instructions in certain instruction sets of interest that provide designers with a means to incorporate newer features into an existing architecture.
In the x86 instruction set architecture, for example, there are no undefined 1-byte opcode states that have not already been used. All 256 opcode states in the primary 1-byte x86 opcode map are taken up with existing instructions. As a result, x86 microprocessor designers must presently make a choice between providing new features and abandoning legacy compatibility. If new programmable features are to be provided, then they must be assigned to opcode states. And if spare opcode states do not remain in an existing instruction set architecture, then some of the existing opcode states must be redefined to provide for the new features. Thus, legacy compatibility is sacrificed in order to provide for new feature growth.
One area of growth that is yet to be addressed in many instruction set architectures is known as selective control of results write back. Many present day application programs exhibit complex signal and data processing algorithms that exercise multiple iterative operations on a single operand in order to produce a meaningful result. In addition, it is often expected that the result will exhibit certain boundary properties, or corner properties, such as being a positive number, a negative number, generating a carry bit, or having an even number of logical ones. Furthermore, as one skilled in the art will appreciate, when execution logic in a present day microprocessor generates a result, the execution logic simultaneously updates a series of condition code bits that are stored in a special register (e.g. a result condition flags register) that indicate the corner properties of the result as described above. Hence, when an operation is executed and a corresponding result is generated, condition code logic in a microprocessor evaluates the corresponding result in view of each of the boundary conditions and sets corresponding bits in the condition codes register for subsequent query by conditional branch instructions. Generally speaking, the flow of application programs frequently is determined based upon whether a result reflects certain boundary conditions as indicated by the state of the condition codes bits.
But what often happens is that the condition bits of a result are checked following an iteration of a program loop to determine if a result has crossed a boundary (e.g., zero, overflow, etc.) or if the result yet remains within a region that is demarcated by the boundary. However, when a following instruction in a program loop examines a condition codes register to determine whether or not the result has crossed the boundary into another region, irreversible damage to the result may have already occurred. One skilled in the art will appreciate that when an operation is performed on an operand, execution logic in the microprocessor generates the result, it evaluates the boundary conditions and updates the condition codes register, and the result is written back into an architectural register specified as a destination for the result. In the case of iterative program loops, the result that is written back into the destination register typically overwrites a result computed during the previous iteration of the program loop. When this occurs, although a programmer is able to subsequently discern that a recently iterated result has crossed a certain boundary, if the boundary defines a region in which the recently iterated result becomes no longer usable, then all previous iterations of the program loop have been wasted.
Therefore, what is needed is a technique that allows a programmer to selectively control the write back of a result that is based upon the state of condition codes corresponding to the result, where the technique is to be provided within an existing microprocessor instruction set architecture, and where the microprocessor instruction set is completely populated with defined opcodes, and where incorporation of the technique allows a conforming microprocessor to retain the capability to execute legacy application programs.